Active antenna arrangement with doherty amplifier

ABSTRACT

A Doherty amplifier ( 100 ) is described which comprises an input terminal ( 102 ) for receiving an input signal ( 101 ) and an output terminal ( 103 ) for providing an amplified signal ( 104 ) of the input signal ( 101 ). The Doherty amplifier is supplied by a first supply voltage and a second supply voltage which have opposite polarities in respect to a reference level.

FIELD OF THE INVENTION

This field of the present application relates in general to a Dohertyamplifier and in particular to an active antenna arrangement comprisingat least a Doherty amplifier. The field of the application also relatesto a method of manufacturing a chipset with a Doherty amplifier and amethod of manufacturing a hybrid module of a Doherty amplifier.

BACKGROUND OF THE INVENTION

The use of mobile communications networks has increased over the lastdecade. Operators of the mobile communications networks have increasedthe number of base stations in order to meet an increased demand forservice by users of the mobile communications networks. The operators ofthe mobile communications network wish to purchase components for thebase stations at a lower price and also wish to reduce the running costsof the base station. Active antenna arrangements with Doherty Amplifiershave proven to meet these goals.

The Doherty amplifier is first known from U.S. Pat. No. 2,658,959 as anefficiency improved amplifier arrangement made of vacuum tubes formodulated signals. Since then the name Doherty amplifier has beenrecognized in the industry to refer to two parallel amplifier stages(vacuum tubes which were subsequently substituted by transistors),whereby a first amplifier stage operates in class AB mode and a secondamplifier stage operates in class C mode. Usually the first stage isbiased in such a way that it linearly amplifies the input signal of thefirst stage from zero excitation to carrier level. The first amplifierstage therefore is also called main stage. The second amplifier stage isbiased in such a way that it amplifies signals above a certainthreshold, i.e. input signals above the carrier level. Therefore it isusually called peak amplifier stage. In order to improve load balancing,the input signals of both amplifiers are shifted in phase so that thephase difference between the input signals of both amplifier stages is90 degrees apart. In this way the phase of the output signals of themain stage and the peak stage are also 90 degrees apart. In order toform the output signal of the Doherty amplifier the phase shifted outputsignals are recombined in-phase.

In the original patent U.S. Pat. No. 2,658,959 the phase shiftingbetween the input signal of the main stage and the input signal of thepeak stage was achieved by a LC-voltage divider between the input of theamplifier arrangement and the input of the main stage; and a CL-voltagedivider between the input of the amplifier arrangement and the input ofthe peak amplifier stage. As a result of this arrangement one inputsignal was retarded by 45 degrees in relation to the input signal of theamplifier arrangement. In contrast hereto the input signal of the otheramplifier was 45 degrees advanced in relation to the input signal. Theoverall effect was to make both amplifiers work at a phase difference of90 degrees.

In the paper “A New High-Efficiency Power Amplifier for ModulatedWaves”, Bell Telephone System Technical Publications B-931 in 1936,Doherty also describes the use of 90 degree networks. FIG. 9 in thispaper depicts two different applications. In the first application theinput signal of the Doherty amplifier is passed through a −90 degreenetwork before it is fed to the input of the first amplifier stage,whereas the input signal of the Doherty amplifier is fed directly to theinput of the second amplifier stage, without applying any phase changes.A second −90 degree network at the output of the second amplifier stageretards the output of the second amplifier stage, so that the outputsignal of first amplifier stage and the output signal of the secondamplifier stage after the second −90 degree network are in-phase and canbe re-combined. A second application depicted in the said figure showshow to use a negative shifting 90 degree network at the input and apositive 90 degree shifting network at the output of the same amplifierstage. By this the phase difference within the same stage is compensatedand the signals of the first and the second stage can be re-combinedin-phase.

The stages of a Doherty amplifier may be formed by bipolar transistorsor field effect transistors (FET). US Patent Application Publication2009/0179702 A1 shows a Doherty amplifier arrangement comprising firstand second bipolar transistors as well as first and second field effecttransistors.

SUMMARY OF THE INVENTION

It is an aspect of the teachings of this application to provide aDoherty amplifier that can be produced at lower cost. The Dohertyamplifier according to the teachings disclosed herein comprises an inputterminal for receiving an input signal and an output terminal forproviding an amplified signal of the input signal. The Doherty amplifieris supplied by a first supply voltage and a second supply voltage whichhave opposite polarities in respect to a reference level. A firsttransistor has a first control input for receiving a first input signalderived from the input signal, a first output, and a first supply inputconnected to the second supply voltage. A second transistor has a secondcontrol input for receiving a second input signal being derived from theinput signal, an output, and a second supply input connected to thesecond supply voltage, wherein the phase of the first input signal andthe phase of the second input signal differ by 90 degrees. A thirdtransistor is connected with a third supply input to the first output ofthe first transistor, and has a third control input connected to commonground or a reference level and has a third output for providing a firstamplified signal of the first input signal. A fourth transistor isconnected with a fourth supply input to the second output of the secondtransistor and has a fourth control input connected to common ground ora reference level and a fourth output for providing a second amplifiedsignal of the second input signal. A phase shifting element is connectedbetween the third output of the third transistor and the fourth outputof the fourth transistor for combining the first amplified signal andthe second amplified signal in-phase thus forming the output signal ofthe Doherty amplifier.

Another aspect of the teachings of this application is that a constantcurrent source is connected to the second output of the secondtransistor and the second emitter of the second transistor.

Another aspect of the teaching of this application is that the presentedDoherty amplifier is incorporated in an active antenna arrangement.

Another aspect of the teaching of this application is a method formanufacturing a Doherty amplifier having an input terminal for receivingan input signal, having an output terminal for providing an amplifiedsignal of the input signal, having a first supply voltage terminal for afirst supply voltage, having a second supply voltage terminal for asecond supply voltage and having a reference terminal for a referencelevel. The method comprises the steps of connecting the input terminalof the Doherty amplifier to a first input of a first phase shiftingelement, connecting a first phase shifting element output of the firstphase shifting element to a first control input of a first transistor,connecting a first supply input of the first transistor to the secondsupply voltage terminal, connecting a second supply input of a secondtransistor to the second supply voltage terminal, connecting a firstoutput of the first transistor to a third supply input of a thirdtransistor, connecting a second output of the second transistor to afourth supply input of a fourth transistor, connecting a third controlinput of the third transistor to a reference terminal or groundterminal, connecting a fourth control input of the fourth transistor toa reference terminal or ground terminal, connecting the fourth output ofthe fourth transistor to a second phase shifting input of a second phaseshifting element, connecting a second phase shifting output of thesecond phase shifting element to the output terminal of the Dohertyamplifier, connecting the fourth output of the fourth transistor to afirst inductor terminal of a inductor, and connecting a second inductorterminal of the inductor to the first supply voltage terminal.

DESCRIPTION OF THE FIGURES

FIG. 1 shows a first aspect of the Doherty amplifier according to thepresent disclosure

FIG. 2 shows a further aspect of the Doherty amplifier according to thepresent disclosure

FIG. 3 shows yet another aspect of the Doherty amplifier according tothe present disclosure

FIG. 4 shows yet another aspect of the Doherty amplifier according tothe present disclosure

FIG. 5 shows a hybrid module incorporating a Doherty amplifier accordingto the present disclosure

FIG. 6 shows a method for manufacturing a Doherty amplifier according tothe present disclosure

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described on the basis of the drawings. Itwill be understood that the embodiments and aspects of the inventiondescribed herein are only examples and do not limit the protective scopeof the claims in any way. The invention is defined by the claims andtheir equivalents. It will be understood that features of one aspect orembodiment of the invention can be combined with a feature of adifferent aspect or aspects and/or embodiments of the invention.

FIG. 1 shows a first aspect of the Doherty amplifier 100 according tothe present disclosure. The Doherty amplifier 100 comprises a firsttransistor Q1, a second transistor Q2, a third transistor Q3, and afourth transistor Q4. The Doherty amplifier 100 is adapted to amplify amodulated radio signal 101 received at an input port 102 of the Dohertyamplifier 100 and to provide an amplified radio signal 104 at an outputport 103 of the Doherty amplifier 100. In this first aspect of thedisclosure the transistors Q1, Q2, Q3, Q4 are all bipolar transistors oftype NPN. For better readability they are referred to as transistorsthroughout the description of FIG. 1.

The input port 102 of the Doherty amplifier 100 is connected to a firstdelay line input 151 of a first λ/4-delay line 150. A first delay lineoutput 152 of the first λ/4-delay line 150 is connected to a first base111 of the first transistor Q1. The first λ/4-delay 150 line is chosensuch that the wavelength λ equals the wavelength of the carrier signalof the modulated radio signal 101. By this the phase of the signalbetween the first delay line input 151 and the first delay line output152 of the first λ/4-delay line 150 is retarded by 90 degrees.

A first emitter 112 of the first transistor Q1 is connected to anegative supply voltage −V_(EE) that is negative in relation to groundGND. The first collector 113 of the first transistor Q1 is connected toa third emitter 132 of the third transistor Q3. The third collector 133of the third transistor Q3 is connected to the output port 103 of theDoherty amplifier 100. The third base 131 of the third transistor Q3 isconnected to ground GND.

The input port 102 of the Doherty amplifier 100 is also connected to asecond base 121 of the second transistor Q2. The second emitter 122 ofthe second transistor Q2 is connected to the negative supply voltage−V_(EE), whereas a second collector of the second transistor Q2 isconnected to a fourth emitter 142 of the fourth transistor Q4. A fourthbase 141 of the fourth transistor Q4 is connected to ground GND. Thefourth collector 143 of the fourth transistor Q4 is connected to a firstinductive element terminal 171 of an inductive element 170. A secondinductive element terminal 172 of the inductive element 170 is connectedto a positive supply voltage +V_(CC). The inductive element 170, forexample a coil serves as a choke allowing direct current to pass whereasthe high impedance for radio frequencies substantially blocks theamplified radio frequency to pass through the inductive element 170.

The common connection of the fourth collector 143 of the fourthtransistor Q4 and the first inductive element terminal 171 of theinductive element 170 is also connected to a second delay line input 161of a second λ/4-delay line 160. A second delay line output 162 of thesecond λ/4-delay line 160 is connected to the output port 103 of theDoherty amplifier 100. The second λ/4-delay 160 line is chosen like thefirst λ/4-delay 150 such that the wavelength A equals the wavelength ofthe carrier signal of the modulated radio signal 101. By this the phaseof the signal between its second delay line input 161 and the seconddelay line output 162 of the second λ/4-delay line 160 is retarded by 90degrees.

In order to achieve a desired output power level at the output port 103the voltage of the positive supply voltage is chosen between +20 Voltsand +28 Volts. The negative supply voltage is chosen in the presentdisclosure in a range between −2 Volts and −3 Volts. The person skilledin the art will appreciated that depending on the chosen output powerand other design constraints the presented values for the positivesupply voltage +V_(CC) and the negative supply voltage −V_(EE) are mereexamples and may have to be chosen differently for other applications ordue to other different technical characteristics of the chosentransistors. For reason of reducing complexity resistors or any otherappropriate means for setting the bias for the first transistor Q1 andthe second transistor Q2 to work as a carrier amplifier and a peakamplifier are not shown, as the person skilled in the art will know howto chose the appropriate means for a given application.

As the radio frequency in current mobile communication systems is in arange from 0.7 GHz to 2.6G Hz the first and second transistors Q1, Q2used in Doherty amplifiers with a supply voltage over 20 Volts mustsatisfy the technical properties of high speed transistors with a highbreakdown voltage, especially a high collector-base breakdown voltage.Transistors having both these properties used specialised technologiesfor their production, for example a Gallium Arsenide, which renders thetransistors relatively expensive. With the arrangement of the third anda fourth transistor Q3, Q4 the first and second transistor Q1, Q2 can beoperated at a relatively low breakdown voltage requirement. Anotheraspect of the third and fourth transistor Q3, Q4 is that the Millereffect of the first and second transistor Q1, Q2 is eliminated, whichincreases the bandwidth of the Doherty amplifier. By this the transistortypes that can be chosen for the first and second transistor Q1, Q2 canbe produced in cheaper technology, such as Silicon Germanium. Althoughthe third and fourth transistor Q3, Q4 have to be adopted to withstandthe high breakdown voltage, due to the fact that the speed requirementis much lower for the third and fourth transistor Q3, Q4 than for thefirst and second transistor Q1, Q2 they may be also produced in acheaper technology, such as Silicon Germanium.

Avoiding the use of specialised technologies may reduce the costs forproduction down to 10% of the costs for the specialised technology.Another advantage of avoiding the specialised technology is that alltransistors can be produced in the same technology. In the event of theintegration of the transistors in a chipset, a higher integration levelwill be achieved.

In the first aspect of the disclosure the transistors Q1, Q2, Q3, Q4 arebipolar transistors of type NPN. In principle the aspect of the presentdisclosure will also work with bipolar transistors of type PNP. Itshould be noted that in this case the polarity of the positive supplyvoltage +V_(CC) and the negative supply voltage −V_(EE) have to bechosen in the opposite way. This aspect of the disclosure is applicableto any type of transistors, such as heterojunction bipolar transistors(HBT) and high electron mobility transistors (HEMT).

In a second aspect of the disclosure a Doherty amplifier 100 is depictedthat uses for the first and second transistor Q1, Q2 transistors of thetype field effect transistor. Apart from a first field effecttransistors FET1 and a second field effect transistor FET2 the secondaspect of the disclosure uses the same elements in the same arrangementas in the first aspect of the disclosure depicted in FIG. 1. As aconsequence the same reference numbers are used in FIG. 2 for the sameelements.

In the Doherty amplifier 100 of the second aspect of the disclosure themodulated input signal 101 is directly fed to a second gate 121 of thesecond field effect transistor FET2 and via the first λ/4-delay line 150to a first gate 111 of the first field effect transistor FET1. A firstsource 112 of the first field effect transistor FET1 and a second source122 of the second field effect transistor FET2 are both connected tonegative supply voltage −V_(EE). A first drain 113 of the first fieldeffect transistor FET1 is connected to the third emitter 132 of thethird transistor Q3. A second drain 123 of the second field effecttransistor FET2 is connected to the fourth emitter 142 of the fourthtransistor Q4.

FIG. 3 shows another aspect of the disclosure. The arrangement issimilar to the arrangement shown in FIG. 1 and the same referencenumbers have been used as in FIG. 1. In addition to the arrangement ofthe first aspect of the disclosure a constant current source circuit I1is connected between the fourth emitter 142 of the fourth transistor Q4and the negative supply voltage −V_(EE) providing a constant current. Inthis aspect of the present disclosure the constant current sourcecircuit I1 stands as an example for all equivalents to constant currentsources. The person skilled in the art may decide for example, that aresistor, although an imperfect constant source, may be sufficient forthe same purpose. The constant current (or substantially constantcurrent in the event of a mere resistor) is chosen such that in theevent the second transistor Q2 is in a non-conductive stage, the currentthat flows through from the fourth collector 143 of the fourthtransistor Q4 to the fourth emitter 142 of the fourth transistor Q4 ispreferably just so high to operate the fourth transistor Q4 beyond inforward region even if Q2 is in cutoff region. When the secondtransistor Q2 is used as a peak power amplifier stage, the constantcurrent source circuit I1 will ensure a fast response of the fourthtransistor Q4 when the second transistor Q2 is driven by an input signalfrom cutoff region to forward region.

FIG. 4 shows another aspect of the disclosure. The arrangement issimilar to the arrangement shown in FIG. 1. Instead of the firstλ/4-delay lines 150 and the second λ/4-delay line 160 quadraturecouplers 180, 190 are used as phase shifting elements. A quadrature,coupler 180, 190 can be either used to split signals or to combinesignals. In power splitting mode a quadrature coupler can receive aninput signal and produces two output signals. The input power is equallydivided between the two signals, but due to the general design principleof a quadrature coupler the two output signals are 90 degrees apart inphase. In power combining mode a quadrature coupler receives two inputsignals and provides a signal that is a combination of its both inputsignals. In the course of combination one of the input signals isretarded by 90 degrees in relation to the other input signal. Often aso-called isolated port is terminated with an internal or externalmatched load.

In FIG. 4 the input signal 101 of the Doherty amplifier 100 is fed to afirst quadrature coupler input port 181 of a first quadrature coupler180, which is operated in power splitting mode. A first quadraturecoupler output port 182 of the first quadrature coupler 180 is connectedto the second base 121 of the second transistor Q2. A second quadraturecoupler output port 183 of the first quadrature coupler 180 is connectedto the first base 111 of the first transistor Q1. A first isolated port184 of the first quadrature coupler 180 is connected via a firstresistor 185 with the reference level GND. The third collector 133 ofthe third transistor Q3 is connected to a second quadrature couplerinput port 192 of a second quadrature coupler 190, which is operated incombining mode. The fourth collector 143 of the fourth transistor Q4 isconnected to a third quadrature coupler input port 191 of the secondquadrature coupler 190. A second isolated port 194 of the secondquadrature coupler 190 is connected via a second resistor 195 to a firstcapacitor terminal of a capacitor 196. A second capacitor terminal ofthe second capacitor 196 is connected with the reference level GND.

The second isolated port 194 is also connected with a third inductiveelement terminal 199 of a second inductive element 197. A fourthinductive element terminal 198 of the second inductive element 197 isconnected to the positive supply voltage +V_(CC). The second inductiveelement 197, for example a coil serves as a choke allowing directcurrent to pass whereas the high impedance for radio frequenciessubstantially blocks the amplified radio frequency signal to passthrough the second inductive element 197. As the capacitor 196 blocksdirect current from flowing to the ground level GND, the positive supplyvoltage +V_(CC) flows unhindered from the second isolated port 194through the seocond quatrature coupler 190 to the second quatratureinput port 192. It serves there as the supply voltage for the thirdtransistor Q3 and the first transistor Q1.

The first resistor 185 and the second resistor 195 are chosen to matchthe impedance of the first quadrature coupler 180 and the secondquadrature coupler 190. As the capacitor 196 has a low impedance forradio signals it does not disturb matching the the second isolated port194 with the second load resistor 195. The first quadrature coupleroutput port 182 and the second quadrature coupler output port 183 of thefirst quadrature coupler 180 and the second quadrature coupler inputport 192 and the third quadrature coupler input port 191 of the secondquadrature coupler 190 are chosen in their order such that the outputsignal at the third quadrature coupler output port 193 of the secondquadrature coupler 190 is an in-phase combination of the respectiveinput signals at the first quadrature coupler output port 182 of thefirst quadrature coupler 180 and the second quadrature coupler outputport 183 of the first quadrature coupler 180.

The use of quadrature couplers 180, 190 reduces the overall space of theDoherty amplifier 100.

Another aspect of the disclosure is the composition of the elements of aDoherty amplifier on a hybrid module 200 as shown in FIG. 5 whichprovides several external terminals. An input terminal 201 for receivingan input signal, an output terminal 202 for providing an amplifiedsignal of the input signal, a first supply voltage terminal 203 for afirst supply voltage, a second supply voltage terminal 204 for secondsupply voltage, and a reference terminal 205 for a reference level GND.

The manufacturing steps of such a hybrid module 200 is shown FIG. 6. Inthe manufacturing process the following steps will be executed:

In a first step 1001 the input terminal 201 of the Doherty amplifierhybrid module 200 is connected to the first phase shifting element input181 of the first phase shifting element 180.

In a second step 1002 the first phase shifting element output 182 of thefirst phase shifting element 180 is connected to the second controlinput 121 of the second transistor Q2.

In a third step 1003 the first supply input 112 of the first transistorQ1 is connected to the second supply voltage terminal 204 of the hybridmodule 200.

In a fourth step 1004 the second supply input 122 of the secondtransistor Q2 is connected to the second supply voltage terminal 204 ofthe hybrid module 200.

In a fifth step 1005 the first output 113 of the first transistor Q1 isconnected to a third supply input 132 of the third transistor Q3.

In a sixth step the second output 123 of the second transistor Q2 isconnected to the fourth supply input 142 of the fourth transistor Q4.

In a seventh step 1007 the third control input 131 of the thirdtransistor Q3 is connected to ground terminal 205 of the hybrid module200.

In an eight step 1008 the fourth control input 141 of the fourthtransistor Q4 is connected to ground terminal 205 of the hybrid module200.

In a ninth step 1009 the fourth output 143 of the fourth transistor Q4is connected to a second phase shifting element input 191 of a secondphase shifting element 190.

In a tenth step 1010 a third phase shifting element output 193 of thesecond phase shifting element 190 is connected to the output terminal205 of the hybrid module 200.

In an eleventh step 1011 the fourth output 143 of the fourth transistorQ4 is connected to a first inductance terminal 171 of a first inductance170.

In a twelfth step a second inductance terminal 172 of the firstinductance 170 is connected to the first supply voltage terminal 203 ofthe hybrid module 200.

The order of the process steps described above were chosen in an orderfollowing roughly the flow of a signal from the input 201 of the hybridmodule 200 to the output 202 of the hybrid module 200. Thus the orderwas thought for illustration purposes only. The person skilled in theart will appreciate that the manufacturing steps can be executed in anyorder.

The present disclosure further relates to a computer program productembedded on a computer readable medium. The computer program productcomprises executable instructions for the manufacture of the Dohertyamplifier of the present disclosure.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample, and not limitation. It will be apparent to persons skilled inthe relevant arts that various changes in form and detail can be madetherein without departing from the scope of the invention. Thus, thepresent invention should not be limited by any of the above-describedexemplary embodiments, but should be defined only in accordance with thefollowing claims and their equivalents.

In addition to using hardware (e.g., within or coupled to a CentralProcessing Unit (“CPU”), microprocessor, microcontroller, digital signalprocessor, processor core, System on chip (“SOC”), or any other device),implementations may also be embodied in software (e.g., computerreadable code, program code, and/or instructions disposed in any form,such as source, object or machine language) disposed, for example, in acomputer usable (e.g., readable) medium configured to store thesoftware. Such software can enable, for example, the function,fabrication, modelling, simulation, description and/or testing of theapparatus and methods described herein. For example, this can beaccomplished through the use of general programming languages (e.g., C,C++), hardware description languages (HDL) including Verilog HDL, VHDL,and so on, or other available programs. Such software can be disposed inany known computer usable medium such as semiconductor, magnetic disk,or optical disc (e.g., CD-ROM, DVD-ROM, etc.). The software can also bedisposed as a computer data signal embodied in a computer usable (e.g.,readable) transmission medium (e.g., carrier wave or any other mediumincluding digital, optical, or analogue-based medium). Embodiments ofthe present invention may include methods of providing the apparatusdescribed herein by providing software describing the apparatus andsubsequently transmitting the software as a computer data signal over acommunication network including the Internet and intranets. It isunderstood that the apparatus and method described herein may beincluded in a semiconductor intellectual property core, such as amicroprocessor core (e.g., embodied in HOL) and transformed to hardwarein the production of integrated circuits. Additionally, the apparatusand methods described herein may be embodied as a combination ofhardware and software. Thus, the present invention should not be limitedby any of the above-described exemplary embodiments, but should bedefined only in accordance with the following claims and theirequivalents.

1. A Doherty amplifier having an input terminal for receiving an inputsignal and having an output terminal for providing an amplified signalof the input signal, the Doherty amplifier being supplied by a firstsupply voltage and a second supply voltage which have oppositepolarities in respect to a reference level, the Doherty amplifierfurther comprising: a first transistor, having a first control input forreceiving a first input signal derived from the input signal, having afirst output, and having a first supply input connected to the secondsupply voltage, a second transistor, having a second control input forreceiving a second input signal being derived from the input signal,having a second output, and having a second supply input connected tothe second supply voltage, wherein the phase of the first input signaland the phase of the second input signal differ by 90 degrees a thirdtransistor, being connected with a third supply input to the firstoutput of the first transistor, and having a third control inputconnected to the reference level and having a third output for providinga first amplified signal of the first input signal a fourth transistor,being connected with a fourth supply input to the second output of thesecond transistor and having a fourth control input connected to thereference level, and having a fourth output for providing a secondamplified signal of the second input signal a phase shifting elementconnected between the third output of the third transistor and thefourth output of the fourth transistor for combining the first amplifiedsignal and the second amplified signal in-phase thus forming the outputsignal of the Doherty amplifier.
 2. The Doherty amplifier according toclaim 1, wherein a constant current source is connected to the secondoutput of the second transistor and the second supply input of thesecond transistor.
 3. The Doherty amplifier according to claim 1 whereinthe first transistor is a bipolar transistor, the first control inputfor receiving the first input signal is the base of the firsttransistor, the first output of the first transistor is the collector ofthe first transistor, and the first supply input is the emitter of thefirst transistor wherein the second transistor is a bipolar transistor,the second control input for receiving the second input signal is thebase of the second transistor, the second output of the secondtransistor is the collector of the second transistor, and the secondsupply input is the emitter of the second transistor.
 4. The Dohertyamplifier according to claim 1 wherein the first transistor is a fieldeffect transistor, the first control input for receiving the first inputsignal is the gate of the first transistor, the first output of thefirst transistor is the drain of the first transistor, and the firstsupply input is the source of the first transistor wherein the secondtransistor is a field effect transistor, the second control input forreceiving the second input signal is the gate of the second transistor,the second output of the second transistor is the drain of the secondtransistor, and the second supply input is the source of the secondtransistor
 5. The Doherty amplifier according to claim 1 wherein thefirst supply voltage is with respect to reference level a positivesupply voltage in the range of 20 Volts to 28 Volts.
 6. The Dohertyamplifier according to claim 1 wherein the second supply valtage is withrespect to the reference level a negative supply voltage in the range of−2 Volts to −3 Volts.
 7. The Doherty amplifier according to claim 1wherein a first λ/4 phase shifting element is inserted between the inputterminal of the Doherty amplifier and the first input of the firsttransistor and wherein a second λ/4 phase shifting element is insertedbetween the third output of the third transistor and the fourth outputof the fourth transistor.
 8. The Doherty amplifier according to claim 6wherein at least one of the first λ/4 phase shifting element or thesecond λ/4 phase shifting element is one of a delay line or a quadraturecoupler.
 9. A chip set comprising a Doherty amplifier having an inputterminal for receiving an input signal and having an output terminal forproviding an amplified signal of the input signal, the Doherty amplifierbeing supplied by a first supply voltage and a second supply voltagewhich have opposite polarities in respect to a reference level, theDoherty amplifier further comprising: a first transistor, having a firstcontrol input for receiving a first input signal derived from the inputsignal, having a first output, and having a first supply input connectedto the second supply voltage, a second transistor, having a secondcontrol input for receiving a second input signal being derived from theinput signal, having a second output, and having a second supply inputconnected to negative supply voltage, wherein the phase of the firstinput signal and the phase of the second input signal differ by 90degrees a third transistor, being connected with a third source supplyinput to the first output of the first transistor, and having a thirdcontrol input connected to common ground and having a third output forproviding a first amplified signal of the first input signal a fourthtransistor, being connected with a fourth supply input to the secondoutput of the second transistor and having a fourth control inputconnected to common ground, and having a fourth output for providing asecond amplified signal of the second input signal a phase shiftingelement connected between the third output of the third transistor andthe fourth output of the fourth transistor for combining the firstamplified signal and the second amplified signal in-phase thus formingthe output signal of the Doherty amplifier.
 10. The chipset according toclaim 9 wherein the chip set is formed by a hybrid circuit.
 11. Anactive antenna array comprising at least one Doherty amplifier having aninput terminal for receiving an input signal and having an outputterminal for providing an amplified signal of the input signal, theDoherty amplifier being supplied by a first supply voltage and a secondsupply voltage which have opposite polarities in respect to a referencelevel, the Doherty amplifier further comprising: a first transistor,having a first control input for receiving a first input signal derivedfrom the input signal, having a first output, and having a first supplyinput connected to the second supply voltage, a second transistor,having a second control input for receiving a second input signal beingderived from the input signal, having an output, and having a secondsupply input connected to the second supply voltage, wherein the phaseof the first input signal and the phase of the second input signaldiffer by 90 degrees a third transistor, being connected with a thirdsupply input to the first output of the first transistor, and having athird control input connected to the reference level and having a thirdoutput for providing a first amplified signal of the first input signala fourth transistor, being connected with a fourth supply input to thesecond output of the second transistor and having a fourth control inputconnected to the reference level, and having a fourth output forproviding a second amplified signal of the second input signal a phaseshifting element connected between the third output of the thirdtransistor and the fourth output of the fourth transistor for combiningthe first amplified signal and the second amplified signal in-phase thusforming the output signal of the Doherty amplifier.
 12. A method formanufacturing a Doherty amplifier having an input terminal for receivingan input signal, having an output terminal for providing an amplifiedsignal of the input signal, having a first supply terminal for a firstsupply voltage, having a second supply terminal for a second supplyvoltage and having a reference terminal for a reference level, themethod comprising the steps of: connecting the input terminal of theDoherty amplifier to a first input of a first phase shifting elementconnecting a first output of the first phase shifting element to a firstcontrol input of a first transistor connecting a first supply input ofthe first transistor to the second supply voltage terminal connecting asecond supply input of a second transistor to the negative supplyvoltage terminal connecting a first output of the first transistor to athird supply input of a third transistor connecting a second output ofthe second transistor to a fourth supply input of a fourth transistorconnecting a third control input of the third transistor to thereference terminal connecting a fourth control input of the fourthtransistor to the reference terminal connecting the fourth output of thefourth transistor to a second input of a second phase shifting elementconnecting a second output of the second phase shifting element to theoutput terminal of the Doherty amplifier connecting the fourth output ofthe fourth transistor to a first inductance terminal of a firstinductance connecting a second inductance terminal of the firstinductance to the first supply voltage terminal.
 13. A computer programproduct comprising a non-transitory computer-usable medium havingcontrol logic stored therein for causing a computer to manufacture aDoherty amplifier having an input terminal for receiving an input signaland having an output terminal for providing an amplified signal of theinput signal, the Doherty amplifier being supplied by a first supplyvoltage and a second supply voltage which have opposite polarities inrespect to a reference level, the Doherty amplifier further comprising:a first transistor, having a first control input for receiving a firstinput signal derived from the input signal, having a first output, andhaving a first supply input connected to the second supply voltage, asecond transistor, having a second control input for receiving a secondinput signal being derived from the input signal, having an output, andhaving a second supply input connected to the second supply voltage,wherein the phase of the first input signal and the phase of the secondinput signal differ by 90 degrees, a third transistor, being connectedwith a third supply input to the first output of the first transistor,and having a third control input connected to the reference level andhaving a third output for providing a first amplified signal of thefirst input signal, a fourth transistor, being connected with a fourthsupply input to the second output of the second transistor and having afourth control input connected to the reference level, and having afourth output for providing a second amplified signal of the secondinput signal; and a phase shifting element connected between the thirdoutput of the third transistor and the fourth output of the fourthtransistor for combining the first amplified signal and the secondamplified signal in-phase thus forming the output signal of the Dohertyamplifier.